With continuous development of semiconductor technology, dimensions of semiconductor devices continue to decrease. The reduction of the critical dimensions of the semiconductor devices means a greater number of transistors can be placed on a single chip, which raises higher requirements for the semiconductor process.
To overcome short-channel effect, suppress leakage current and lower threshold voltage of the transistor, a high dielectric constant insulating layer and metal gate (High-K metal gate, HKMG) technology has been developed. In the HKMG technology, a high-K gate dielectric layer is used to replace a traditional SiO2 gate dielectric layer, and a metal material gate is used to replace a silicon material gate. When forming a HKMG structure by a gate-last process, because the metal gate is formed after forming source and drain doped regions, the metal gate is not under the high temperature used for forming the source and drain doped regions, the metal gate is not easily deformed. The gate-last process is used to form the HKMG structure.
The gate-last process for forming the HKMG structure includes: forming a dummy gate structure on a substrate; forming source and drain doped regions in the substrate on both sides of the dummy gate structure; forming a dielectric layer to cover top and sidewalls of the dummy gate structure; removing the dielectric layer on the top of the dummy gate structure to form an isolation dielectric layer; and removing the dummy gate structure.
However, when removing the dielectric layer on the top of the dummy gate structure, the insulation performance of the isolation dielectric layer formed between transistors is easily degraded, and the performance of the formed semiconductor structure is affected. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.